1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device including memory cells that require a refresh operation for retaining information.
2. Description of Related Art
DRAMs (Dynamic Random Access Memory) that are representative semiconductor devices are volatile semiconductor memory devices. In DRAMs, because information is stored as an electric charge in capacitors that are included in memory cells, information is lost due to a leakage current if a refresh operation is not performed periodically. Therefore, it is necessary to refresh all memory cells before the information is lost due to the leakage current. A period (=tREF) of 64 milliseconds (msec) is defined as a standard for refreshing all the memory cells. Auto refresh commands issued by a controller in succession in a time series are issued in such a manner that all word lines associated with all the memory cells are selected within the period of 64 msec. It is not necessary to input a refresh address when issuing the auto refresh commands. That is, a refresh address associated with a word line to be refreshed is automatically generated by a refresh address counter provided in the DRAMs.
For example, if there are 8192 refresh addresses (=8192 word lines), the controller issues an auto refresh command 8192 times within a period of 64 msec. Therefore, one cycle of a count value of the refresh address counter is completed in 64 msec. As long as the auto refresh command is issued 8192 times within the period of 64 msec, the auto refresh commands can be issued at an arbitrary timing. As a first example, the auto refresh commands can be issued at substantially equal intervals (an interval of approximately 7.8 microseconds (μsec)) within the period of 64 msec. As a second example, the auto refresh commands can be issued 8192 times concentrically in a fixed period of time within the period of 64 msec. The command issuing method in the first example is sometimes called “distributed refresh method” and that in the second example is called “concentrated refresh method”. In the concentrated refresh method, the interval for issuing the auto refresh commands needs to be equal to or greater than a minimum issue interval tRFC defined according to specifications (such as 100 nanoseconds (nsec)). However, the concentrated refresh method may not be used for some specifications.
A mode described above in which the refresh operation is performed in response to the auto refresh command is called “auto refresh mode”. On the other hand, unlike the auto refresh mode, there is a self refresh mode that automatically (autonomously) performs a periodic refresh operation in a semiconductor device. Once entered in the self refresh mode, the refresh operation is automatically performed at the interval of approximately 7.8 μsec based on the distributed refresh method using a timer (an internal timer) provided in the semiconductor device.
Meanwhile, among memory cells, some memory cells have a shorter information retaining time than the rest of the memory cells (which are in majority). A refresh operation needs to be performed more frequently for such memory cells with a shorter information retaining time as compared to the other memory cells to prevent loss of information. For example, the third embodiment of Japanese Patent Application Laid-open No. 2006-323909 discloses a method in which, when a refresh address indicated by a refresh address counter corresponds to a predetermined value, a refresh operation is performed for memory cells with a shorter information retaining time instead of for a memory cell actually indicated by the refresh address in the refresh address counter. The refresh operation is performed for the refresh address actually indicated by the refresh address counter in response to the auto refresh command that is issued after the refresh operation for the memory cell with a shorter information retaining time is performed. Because the refresh operation of the memory cell with a shorter information retaining time is periodically interrupted by the refresh operation of the normal memory cells, the memory cell with a shorter information retaining time can be frequently refreshed.
However, in the method disclosed in Japanese Patent Application Laid-open No. 2006-323909, because the refresh operation of the memory cell with a shorter information retaining time is periodically interrupted, the refresh operation cannot be completed for all refresh addresses only by issuing the auto refresh command by a controller strictly 8192 times within a period of 64 msec. That is, assuming that the number of the refresh operation that is interrupted during one counting cycle of the refresh counter is m, the refresh operation cannot be completed for all refresh addresses unless the auto refresh command is issued 8192+m times. That is, the refresh operation cannot be performed for m addresses by only issuing the auto refresh commands 8192 times.
Note that such a problem does not occur in the distributed refresh method or in the self refresh mode based on the distributed refresh method. This is because, in the distributed refresh method and the self refresh mode based on the distributed refresh method, the refresh operation is performed at substantially equal intervals. Therefore, a length of a refresh cycle for each refresh address is increased only by a small extent (64 msec+α), even if the refresh operation needs to be performed 8192+m times for completing the refresh operation for all refresh addresses.
On the other hand, in the concentrated refresh method, because the auto refresh command is issued a plurality of times all at once within a fixed period of time, memory cells that are not refreshed during the period when the auto refresh commands are issued are not refreshed until after approximately 64 msec have elapsed. This means that the refresh interval is approximately doubled (128 msec) for the m refresh addresses. As a result, there is a possibility that information cannot be retained properly.
The problem described above is not limited to DRAMs, also occurs in all semiconductor devices that require a refresh operation due to the memory cell configuration thereof.